News Archive - Page 21 of 51 - Accelerate Energy Efficient SoC designs

Save up to 20 % of silicon area with our standard cell library SESAME uHD

For integrated circuits with really high volumes, such as MCUs, SESAME uHD (ultra High Density), the flagship product in Dolphin Integration’s standard cell library offering, is paramount to decrease die costs. It stars its patented pulsed latches as « Spinner Cells » instead of standard D-flip flops, openly documented in “Thorough validation: the conundrum of Pulsed latch […]

Save up to 20 % of silicon area with our standard cell library SESAME uHD Read More »

PWM audio D/A converter: cost breaking while maintaining performances
P. Giletti & V. Richard

Audio electronic systems are facing major changes since the rising of ubiquitous devices using voice capabilities. Audio processing combined with high performance converters is becoming the critical contributor to deliver the greatest sound experience. This has led System-on-Chip (SoC) providers and Semiconductor IP suppliers to find the best compromise between cost, performance and flexibility. To

PWM audio D/A converter: cost breaking while maintaining performances
P. Giletti & V. Richard Read More »

Dolphin Integration’s asynchronous standard cell libraries, developed in the frame of LISA Project
Univ. Grenoble Alpes, TIMA Laboratory

High-level synthesis for event-based systems Second International Conference on Event-Based Control, Communications, and Signal Processing (EBCCSP 2016), Jun 2016, Krakow, Poland. This paper envisions a design flow for empowering designers in the fast development of low-power event-driven processing chains. This flow takes advantage of level-crossing sampling schemes and asynchronous circuitry. Event-driven paradigm allows better-than-worst-case performance

Dolphin Integration’s asynchronous standard cell libraries, developed in the frame of LISA Project
Univ. Grenoble Alpes, TIMA Laboratory Read More »

Do not miss the Green Thursday offering for ultra Low-Power SoCs at 55 nm…

Leading-edge More-Than-Moore process variants at 55 nm for the challenges of IoT and wearable devices deserve equally state-of-the-art low power design methodologies: it involves Silicon IPs for embedding the Power Regulation Network and for the SoC Mode Control Network, together with the transfer of know-how to ensure a safe and smooth design-in. Designers of low-power

Do not miss the Green Thursday offering for ultra Low-Power SoCs at 55 nm… Read More »

Pushing SoC optimization to the next level with all risks managed

Minimizing the PCB footprint and the BoM cost implies embedding the Power Regulation Network (PRNet) in the SoC. Meanwhile, minimizing drastically the SoC power consumption involves implementing several modes of activity to turn on and off different functions of the SoC, which generates noise on the supply lines during mode switching. Dolphin Integration is

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Introduction to WhisperTrigger, a breakthrough Voice Activity Detector

Interview at DAC 2016, Austin Vincent Richard, Product Marketing Manager for Audio IPs

Introduction to WhisperTrigger, a breakthrough Voice Activity Detector Read More »

Net profit of € 0.4 M for fiscal year closed on march 31, 2016

Upon its board of directors meeting having closed its accounts, the company announces its financial results of the fiscal year F-16 closed on March 31, and its perspectives. Results on March 31, 2016 The final consolidated sales turnover of fiscal year F-16 reaches the amount of € 14,581k, -2% compared to the € 14,917 k

Net profit of € 0.4 M for fiscal year closed on march 31, 2016 Read More »

Mixed simulator SMASH™ coupled with SILVACO Variation Manager

Silvaco today announced that Dolphin Integration, a leading provider of power and density optimized memory silicon IP, has selected Silvaco Variation Manager TM, coupled with its mixed-signal simulator SMASH™ to perform critical variability analysis and reliability qualification on SRAM memories designed using advanced process technologies. Read this press announcement on Silvaco website… I want to

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A Novel High-Voltage 5.5 V Resilient, Floating and Full-Scale 3.3 V Pulse-Triggered Level-Shifter
Nicolas Laflamme-Mayer and Mathieu Renaud

This paper presents a novel 5.5 V resilient Pulse-Triggered-Level-Shifter (PTLS) with enhanced toggling speed. This PTLS is a based on a cascoded High-Voltage (HV) level-shifters and only uses 3.3 V, near minimum size, CMOS transistors. This HV level-shifter generates both floating and a full-scale output signals and is able to operate under supplies from 2.6

A Novel High-Voltage 5.5 V Resilient, Floating and Full-Scale 3.3 V Pulse-Triggered Level-Shifter
Nicolas Laflamme-Mayer and Mathieu Renaud Read More »

Methodology to lower supply voltage of standard cell libraries
B. Arricca

Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use. Decreasing the supply voltage will

Methodology to lower supply voltage of standard cell libraries
B. Arricca Read More »

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