News Archive - Page 38 of 51 - Accelerate Energy Efficient SoC designs

Spinner System by Dolphin Integration: optimized design and integration methodology based on pulsed latch for drastic area reduction in logic designs
L.Jure

Spinner System by Dolphin Integration: optimized design and integration methodology based on pulsed latch for drastic area reduction in logic designs Lionel JURE Systems-on-a-chip (SoC) design complexity is continuously increasing over the years, and 100 Million gates circuits are now taping out. Additionally, the logic gate count has evolved so as to represent […]

Spinner System by Dolphin Integration: optimized design and integration methodology based on pulsed latch for drastic area reduction in logic designs
L.Jure Read More »

CURRENT FINANCIAL SITUATION – INVITATION TO THE MIXED GENERAL ASSEMBLY OF FEBRUARY 13, 2013

The corporation informs shareholders that their statutory auditors have triggered a warning procedure (phase 3) received on January 14, 2013, due to the financial situation. In this context, top management have immediately gathered the board of directors for preparing a report in response, to address the whole set of actions which they intend to put

CURRENT FINANCIAL SITUATION – INVITATION TO THE MIXED GENERAL ASSEMBLY OF FEBRUARY 13, 2013 Read More »

Faster and safer design for integration presentation of power-optimized SoCs
IP SoC 2012, Grenoble, France
L.Engels, A.Bonzo, G.Gimenez, A.Lacourse, F.Darve

Abstract The construction of low-power islets through: The optimization of the power management network, early in the design flow (i.e. before RTL design), through simulation with behavioral models using rough power consumption estimations. .. And all along the low-power design flow. The implementation of power islets with specific innovative cell and automatic script to handle

Faster and safer design for integration presentation of power-optimized SoCs
IP SoC 2012, Grenoble, France
L.Engels, A.Bonzo, G.Gimenez, A.Lacourse, F.Darve Read More »

How to define a robust and power-optimized power management architecture
IP SoC 2012, Grenoble, France
S.Genevey

Abstract Context: SoCs complexity increase with constraint of power consumption reduction. Solution to reduce power consumption: SoC partitioning in power and voltage islets with several states of activity. Issue to solve: properly select the power management network (PMNet) including power regulators, external and internal capacitors to sustain the voltage drops caused by mode transitions. Traps:

How to define a robust and power-optimized power management architecture
IP SoC 2012, Grenoble, France
S.Genevey Read More »

IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring
IEEE 12th International Conference on BioInformatics and BioEngineering
F.Masson, M.Milis, K.Michaelides, A.Kounoudes,…

IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring: Research project for the benefit of specific groups (FP7, Capacities) IEEE 12th International Conference on BioInformatics and BioEngineering Milis, M.; Michaelides, K.; Kounoudes, A.; Ansaloni, G.; Atienza, D.; Giroud, F.; Ruedi, P.; Masson, F. The objective of the IcyHeart project is

IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring
IEEE 12th International Conference on BioInformatics and BioEngineering
F.Masson, M.Milis, K.Michaelides, A.Kounoudes,… Read More »

Period Deviation Tolerance Templates: A Novel Approach to Evaluation and Specification of Self-Synchronizing Audio Converters
AES Convention:133 – Paper Number: 8729
F.Legray, T.Heeb, S.Genevey, H.Kuo

Period Deviation Tolerance Templates: A Novel Approach to Evaluation and Specification of Self-Synchronizing Audio Converters AES Convention:133 (October 2012) – Paper Number: 8729 Legray, Francis; Heeb, Thierry; Genevey, Sebastien; Kuo, Hugo Subject: Amplifiers, Transducers, and Equipment Self-synchronizing converters represent an elegant and cost effective solution for audio functionality integration into SoC (System-on-Chip) as they integrate

Period Deviation Tolerance Templates: A Novel Approach to Evaluation and Specification of Self-Synchronizing Audio Converters
AES Convention:133 – Paper Number: 8729
F.Legray, T.Heeb, S.Genevey, H.Kuo Read More »

Automated Test Bench for high resolution audio CODEC
user case studies, National Instruments France -Winner of the best 2012 applications in the category of Instrumentation/ electronic test – P.30
C.Gaillard

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Automated Test Bench for high resolution audio CODEC
user case studies, National Instruments France -Winner of the best 2012 applications in the category of Instrumentation/ electronic test – P.30
C.Gaillard Read More »

A Breakthrough in Logic Design Drastically Improving Performances from 65 55 nm LP and Below
TSMC 2012 Open Innovation Platform® Ecosystem Forum
E.Bernard-Moulin, I.Sever

Paper available for download on TSMC website

A Breakthrough in Logic Design Drastically Improving Performances from 65 55 nm LP and Below
TSMC 2012 Open Innovation Platform® Ecosystem Forum
E.Bernard-Moulin, I.Sever Read More »

Novel Low-Power Audio CODEC from 180nm to 28nm with Moore and More!
TSMC 2012 Open Innovation Platform® Ecosystem Forum
F.Renoux, H.Kuo, H.L.Wang

Paper available for download on TSMC website

Novel Low-Power Audio CODEC from 180nm to 28nm with Moore and More!
TSMC 2012 Open Innovation Platform® Ecosystem Forum
F.Renoux, H.Kuo, H.L.Wang Read More »

A first algorithmic construction of low-power islets
IP-SoC Shanghai Event
L.Engels

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A first algorithmic construction of low-power islets
IP-SoC Shanghai Event
L.Engels Read More »

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