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DOLPHIN Integration and TexEDA Design announce their cooperation, delivering a complete and attractive EDA flow embedding SMASH as LaySim into LayTools

Dolphin Integration SA and TexEDA Design Inc announce today that their EDA solutions for logic & mixed-signal simulation, and for custom integrated circuit design, have been closely coupled and bundled to enable a complete and consistent flow. LaySim is offered within the LayTools IC design suite, as either a comprehensive device-level simulator (Spice compatible) or […]

DOLPHIN Integration and TexEDA Design announce their cooperation, delivering a complete and attractive EDA flow embedding SMASH as LaySim into LayTools Read More »

DOLPHIN Integration and Infolytica Corporation enable mechatronic system simulation using MagNet and MotorSolve coupled with SMASH

DOLPHIN Integration SA and Infolytica Corporation announce today that their solutions for mixed signal simulation and electromagnetic field simulation can now work together to perform powerful mechatronic system simulation. SMASH, from DOLPHIN Integration, can directly simulate response surface models of electric motors generated in VHDL-AMS by MagNet or MotorSolve, from Infolytica, and can perform a

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Guidelines for Verilog-A Compact Model Coding
Nanotech 2010 Vol. 2, pp. 821-824
G. Depeyrot, F. Poullet and B. Dumas

Guidelines for Verilog-A Compact Model Coding Nanotech 2010 Vol. 2, pp. 821-824, June 2010 G. Depeyrot, F. Poullet and B. Dumas Keywords: Verilog-A, compact model, SPICE Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for

Guidelines for Verilog-A Compact Model Coding
Nanotech 2010 Vol. 2, pp. 821-824
G. Depeyrot, F. Poullet and B. Dumas
Read More »

Guidelines for Verilog-A Compact Model Coding
Nanotech 2010 Vol. 2, pp. 821-824, June 2010
G. Depeyrot, F. Poullet and B. Dumas

Keywords: Verilog-A, compact model, SPICE Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for both simulation and synthesis (IEEE1364-2001 and IEEE 1364.1-2002), the Verilog-AMS hardware description language includes extensions dedicated to compact modeling, as a

Guidelines for Verilog-A Compact Model Coding
Nanotech 2010 Vol. 2, pp. 821-824, June 2010
G. Depeyrot, F. Poullet and B. Dumas
Read More »

Multiplexed Energy Metering AFEs Ease ASIC Integration and Provide Significant Cost Reduction
C.Domingues
June 2010 GSA Forum

Smart electric meters are fundamental to the successful deployment of smart grid technology, as they improve grid reliability and user consumption control and reduce electricity theft. The variety of consumers’ emerging needs requires a much wider offering of energy metering systems-on-chip (SOCs), paving the way for more fabless companies to enter the energy measurement field.

Multiplexed Energy Metering AFEs Ease ASIC Integration and Provide Significant Cost Reduction
C.Domingues
June 2010 GSA Forum
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